The present invention relates generally to switches. More specifically, the present invention relates to isochronous queue and buffer management in switches.
The IEEE Standard for a High Performance Serial Bus, IEEE Std. 1394-1995 published Aug. 30, 1996 (1394-1995 Standard) and its progeny provide a high speed serial protocol which permits implementation of high speed data transfers. The existing progeny includes P1394a Draft Standard for a High Performance Serial Bus (1394a Standard) and P1394b Draft Standard for a High Performance Serial Bus (1394b Standard). Generically, systems implementing 1394-1995, 1394a, 1394b or subsequent revisions and modifications thereof are referred to herein as 1394 systems.
The IEEE 1394 standard is an international standard for implementing a high-speed serial bus architecture, which supports both asynchronous and isochronous format data transfers. The IEEE 1394 standard defines a bus as a non-cyclic interconnect. Within a non-cyclic interconnect, devices may not be connected together so as to create loops.
In networks, switches filter and forward packets between local area network segments. In packet switching, packets are individually routed between nodes with no previously established communication path. An algorithm is used to route packets to their destination through the most expedient route. The destination computer reassembles the packets in their appropriate order. Packet switching optimizes the use of bandwidth available in a network and minimizes the latency (the time it takes for a packet to cross a network connection, from sender to receiver).
In a 1394 network with multiple 1394 buses and 1394 switches, all the 1394 buses should be synchronous. But due to cycle skewing, the cycle start packets are not all generated at the same time in different 1394 buses. Cycle skewing occurs when a large asynchronous packet is sent over a bus and the large packet is late, which may delay the start of the next cycle.
In a switch, there may be packets arriving from different ingress ports routed to one egress port. Because of cycle skewing, a packet from one cycle may arrive in the egress port after a packet from a subsequent cycle.
Packets being switched may also be transmitted out of order from the switch because a first packet arriving before a second packet at a switch may not be completely received before the second packet is completely received. Thus, the second packet would be sent out before the first packet because the second packet was completely received before the first packet.
A method comprising initializing an eligibility bit map and determining whether at least one eligible route has required resources available is disclosed.